A digital-to-analog converter, or DAC, converts a digital input into an analog output signal, such as a current or voltage. The digital input may be, for example, a digital word. There are several conventional architectures used for DACs.
FIG. 1 shows the general architecture for a conventional form of a binary-weighted, current-mode, DAC 100. Such a DAC includes n binary-weighted current sources 101, where n is the number of bits in the DAC 100. Each current source 101 is controlled by a switch 102, such as a transmission gate. Hence, in the four-bit example of FIG. 1, four binary-weighted copies of the least-significant element, represented by the current I0, are added to the output in any combination, under the control of a four-bit digital input word. Thus, the output may vary from 0 to I0×(24−1).
But there is a significant drawback with the architecture 100 in FIG. 1. That is, any of the weighted sources 101 can be in error by a particular error factor. Consequently, for certain error factors, the slope of the current-vs-code characteristic could reverse. If the slope changes from positive to negative, or vice versa, then the current-vs-code function is not monotonic. For example, if the 8I0 source in FIG. 1 is 15% low, then the outputs for codes 7 and 8 will be 7I0 and 6.8I0 instead of 7I0 and 8I0. Since 6.8I0 is less than 7I0, then the slope of the function will have decreased whereas the function should have increased to 8I0.
In general, the overall matching requirement for monotonicity is that the error factor must be less than the quotient of the least-significant bit divided by the most-significant bit. Non-monotonicity may cause harmonic distortion in DACs used for analog signals, and it can also defeat other algorithms, such as an algorithm for offset correction. This matching problem limits binary DACs that are like the DAC illustrated in FIG. 1 to about eight bits of resolution.
One conventional way of ensuring monotonicity is to utilize a thermometer-coded, current-mode DAC 200, such as the four-bit example depicted in FIG. 2. The thermometer-coded, current-mode DAC 200 includes 2n−1 current sources 201, where n is the number of bits in the DAC 200. Each current source 201 is controlled by a switch 202, such as a transmission gate. Each current source 201 provides a current with a value equal to I0, the least-significant bit. Accordingly, and as shown in FIG. 2, a single copy of I0 is added to the output for each increase in code. Because none of the copies can be negative, monotonicity is ensured. This solution, however, requires a large amount of overhead, in the form of decoding logic and switching, to control the 2n−1 copies of I0. Thus, like the architecture 100 of FIG. 1, DACs with the architecture 200 of FIG. 2 are also usually limited to 8 bits or less.
A combination of a thermometer-coded architecture with other architectures can be used to relieve the tradeoff between overhead and matching for monotonicity. For example, as shown in FIG. 3, a conventional form of a thermometer-coded, current-mode DAC 300 may include a divider 303 for each current source 301. Except for the divider for the highest code, each divider 303 is controlled by two switches 302, which may be, for example, transmission gates. The divider for the highest code, code 8 in the example of FIG. 3, is controlled by a single switch 302 or transmission gate.
In the architecture of FIG. 3, when activated, the leftmost switch in the illustrated pair of switches 302 for each segment allows the full 2I0 current to pass to the output. When activated, the rightmost switch for each segment allows the full 2I0 current to pass to the divider. If neither switch is activated in the pair of switches 302, essentially none of the 2I0 current for that segment passes to the output. Hence, in the four-bit example of FIG. 3, 2n-1 copies of 2I0 are controlled by thermometer logic segments. Each copy is followed by a divider 303 to divide the current by two. Therefore, the output of each segment can be 0, I0, or 2I0 by operation of the switches 302.
Since the dividers 303 do not create scaled copies of I0, but only split it into portions, monotonicity is still ensured with this architecture 300. Only half of the 2I0 unit sources and logic are required as compared to the full thermometer DAC, such as the DAC 200 of FIG. 2. Note that the 2I0 copy for the highest code, code 8 in the example of FIG. 3, is never switched fully to the output in this binary example. Thus, the output of the last segment can be 0 or I0, but not 2I0.
The architecture 300 of FIG. 3 can be simplified to use a single divider since only one copy of 2I0 is treated at a time. Thus, as shown in FIG. 4, a conventional form of a thermometer-coded, current-mode DAC 400 may include a single divider 403 that operates on each current source 401. Except for the current source for the highest code, each current source 401 is controlled by two switches 402 or transmission gates. The current source for the highest code, code 8 in the example of FIG. 4, is controlled by a single switch 402 or transmission gate. The switches operate generally as described above for FIG. 3.
The architectures of FIGS. 3 and 4, though, suffer from a limited set of possible resolution values, dependent only on the number of bits in the DAC 300 or the DAC 400.
Embodiments of the invention address these and other issues in the prior art.